1. Field of the Invention
The present invention relates to a processing system in the semiconductor manufacturing field, and particularly to a processing system of a linear tool.
2. Description of the Related Arts
In a processing system of a semiconductor, a processing system having a structure called as a cluster tool has been widely used. The cluster tool involves a problem that a large space is required to install a processing system, and the required space becomes larger along with the increased diameter of a wafer. Thus, there has been proposed a processing system having a structure called as a linear tool which can be installed even in a small space (see Japanese Unexamined Patent Application Publication No. 2007-511104).
The cluster tool is different from the linear tool in the structure of an internal carrying region which carries a wafer into a processing module and carries a wafer out of a processing module. The cluster tool generally has one carrying robot which carries a wafer in the internal carrying region, and one carrying robot carries a wafer between a load lock serving as a carrying-in/carrying-out port for the internal carrying region and the processing modules. On the other hand, the linear tool has plural carrying robots arranged in the internal carrying region, allows a wafer to be delivered and received between the plural carrying robots, and allows a wafer to be carried between the load lock and the processing modules. However, the carrying robot engaged in carriage differs depending on the position of the processing module to which a wafer is carried. Depending on the position of the processing module, a wafer can be carried by only one carrying robot, or cannot be carried unless the wafer goes through the plural carrying robots.
Further, it is important to improve a throughout in the processing system of a semiconductor. A general processing system includes plural processing modules, and plural wafers are processed in parallel. At this time, the throughput is deteriorated unless the carrying robots sequentially carry the plural wafers. Accordingly, there is known a scheduling method as a method of improving the throughput. In the scheduling method, the timing of carrying and processing each wafer is calculated so as to increase the throughput in consideration of restriction of operations of the carrying robots, and each wafer is carried in accordance with the calculated timing (see Japanese Unexamined Patent Application Publication No. 2002-511193).
In the scheduling method, when a carrying route is provided, the timing of carrying and processing a wafer is calculated so as to improve the throughput on the carrying route. Here, the carrying route means a direction ranging from where a processing target wafer is carried into the processing system to where the wafer is carried out of the processing system after the wafer is processed in the processing modules. The carrying route is determined if a carrying-in port, a processing module to which the wafer is carried, and a carrying-out port are determined. Especially, in the case of a processing system including plural processing modules, if a processing module to which the wafer is carried is not determined for each wafer to be carried, the carrying route is not determined and the scheduling cannot be performed. As a method of determining the processing module to which the wafer is carried, there is known a method in which the processing modules are assigned to a wafer to be carried in ascending order of the completion time of the process (Japanese Patent Application Laid-Open Publication No. H10-189687).